abeltyukov
Newbie level 1
Hi,
I need to design a circuit using 2 positive edge-triggered t flip flops w/synchronous active high reset and CE. The inputs that I am given are INPUT, CLR and CLK and the outputs are Q0, Q1 and RCO. Here's what I have for the code so far:
I need to add code to my design to generate the flip flop excitations (CE0 and CE1) and the output (RCO). This is the part I am getting stuck on. Did I do the right thing and replace <clock enable> in the skeleton code for the t flip flop with CE0 and CE1? Also, should I declare CE0 and CE1 as signals like I did above? I am not sure how to generate CE0 and CE1 excitations but I was thinking something along the lines of CE0 <= CLK and INPUT. Is that correct? If so, would I do CE1 <= CLK and Q0? Where does RCO come in in all of this?
Thanks!
I need to design a circuit using 2 positive edge-triggered t flip flops w/synchronous active high reset and CE. The inputs that I am given are INPUT, CLR and CLK and the outputs are Q0, Q1 and RCO. Here's what I have for the code so far:
Code:
entity sequential is
Port ( INPUT : in STD_LOGIC;
CLR : in STD_LOGIC;
CLK : in STD_LOGIC;
Q0 : buffer STD_LOGIC;
Q1 : buffer STD_LOGIC;
RCO : out STD_LOGIC);
end sequential;
architecture Behavioral of sequential is
signal CE0: STD_LOGIC;
signal CE1: STD_LOGIC;
begin
process (CLK)
begin
if CLK'event and CLK='1' then
if CLR='1' then
Q0 <= '0';
elsif CE0 ='1' then
Q0 <= not(Q0);
end if;
end if;
end process;
process (CLK)
begin
if CLK'event and CLK='1' then
if CLR='1' then
Q1 <= '0';
elsif CE1 ='1' then
Q1 <= not(Q1);
end if;
end if;
end process;
end Behavioral;I need to add code to my design to generate the flip flop excitations (CE0 and CE1) and the output (RCO). This is the part I am getting stuck on. Did I do the right thing and replace <clock enable> in the skeleton code for the t flip flop with CE0 and CE1? Also, should I declare CE0 and CE1 as signals like I did above? I am not sure how to generate CE0 and CE1 excitations but I was thinking something along the lines of CE0 <= CLK and INPUT. Is that correct? If so, would I do CE1 <= CLK and Q0? Where does RCO come in in all of this?
Thanks!