Basit Mehmood
Newbie
What happened if we use blocking assignment in sequential circuit like flip-flop?
I mean is following code correct or not?
I mean is following code correct or not?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 module dff (q, qn, d, clk); input d, clk; output q, qn; reg q, qn; always @(posedge clk) begin q = d; qn = ~d; end endmodule
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