sensitivity list

[Balaji Chirumamilla]

can i use reset in sensitivity list like this.............?




here i want to generate one signal so that it will behave exactly like reset with out any delay's and and i want to generate one flag which tells that reset operation was done,

DOUBT: as i am new to verilog, here i have doubt wheather this code is synthasizable or not................................?

please clarify it




DESIGN

module copy_reset(clk,reset,copy,copy1,copy2);
input clk;
input reset;

output copy;
output copy1;
output copy2;

reg copy;
reg copy1;
reg copy2;

always@(reset)
begin
if (!reset)
copy<=1'b0;
else
copy<=1'b1;
end

always@(posedge clk or negedge reset)
begin
if(!reset)
copy1<=1'b0;
else
copy1<=copy;
end

always@(posedge clk or negedge reset)
begin
if(!reset)
copy2<=1'b0;
else
copy2<=copy1;
end

endmodule

*******************************************************************************************************************

TESTBENCH



module copy_reset_tb();
reg clk;
reg reset;

wire copy;
wire copy1;
wire copy2;

copy_reset copy_reset_i(.clk(clk),
.reset(reset),
.copy(copy),
.copy1(copy1),
.copy2(copy2));



initial
begin
clk=1'b0;
reset=1'b0;
end

always #5 clk=~clk;

initial
begin
#8;
@(posedge clk);
reset=1'b1;

#18;
reset=1'b0;

#8;
@(posedge clk);
reset=1'b1;
end

initial
begin
#1500 $finish;
end
endmodule