self synchronous scrambler - VHDL

[ducna]

scrambler vhdl

I am writing a program about seft synchronous scrambler (meaning that not need synchronization - data stream (A)-> scrambler -> descramber -> restore the same origin (A)) with generator polynomial : x^7 + x^4 +1 but when simulation , i see dataout not the same data in, can anyone help me, my code

scrambler.vhd

--Data randomizer (scrambler)
--Generator polynomial R(x) = x^7 + x^4 + 1
Library ieee;
Use ieee.std_logic_1164.all;


entity scrambler is
port(
reset : in std_logic;
datain : in std_logic; -- input bit
clock : in std_logic; -- data shift clock
-- scrambled output
dataout : out std_logic
);
end scrambler;

architecture behaviour of scrambler is
signal shift_reg: std_logic_vector(6 downto 0); -- shift register
signal dout : std_logic;
begin
process(clock,reset, datain)
begin
if reset = '1' then
shift_reg <= (others=>'1');
dout <= datain;
elsif (clock'event and clock='1') then
dout <= datain xor shift_reg(6) xor shift_reg(3);
shift_reg(0) <= dout;
shift_reg(1) <= shift_reg(0);
shift_reg(2) <= shift_reg(1);
shift_reg(3) <= shift_reg(2);
shift_reg(4) <= shift_reg(3);
shift_reg(5) <= shift_reg(4);
shift_reg(6) <= shift_reg(5);
end if;
end process;

dataout <= dout;

end behaviour;

descrambler

Library ieee;
Use ieee.std_logic_1164.all;

entity descram is
port(
reset : in std_logic;
datain : in std_logic; -- input bit
clock : in std_logic; -- data shift clock
-- descrambled output bit
dataout : out std_logic
);
end descram;

architecture behaviour of descram is
signal shift_reg: std_logic_vector(6 downto 0); -- shift register
begin
process(reset, clock, datain)
begin
if reset = '1' then
shift_reg <= (others=>'1');
dataout <= datain;
elsif (clock'event and clock='1') then
shift_reg(0) <= datain;
shift_reg(1) <= shift_reg(0);
shift_reg(2) <= shift_reg(1);
shift_reg(3) <= shift_reg(2);
shift_reg(4) <= shift_reg(3);
shift_reg(5) <= shift_reg(4);
shift_reg(6) <= shift_reg(5);

dataout <= datain xor shift_reg(6) xor shift_reg(3);
end if;
end process;
end behaviour;

and testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_scram_vhd IS
END tb_scram_vhd;

ARCHITECTURE behavior OF tb_scram_vhd IS
COMPONENT scrambler
PORT(
reset : IN std_logic;
datain : IN std_logic;
clock : IN std_logic;
dataout : OUT std_logic
);
END COMPONENT;

COMPONENT descram
PORT(
reset : IN std_logic;
datain : IN std_logic;
clock : IN std_logic;
dataout : OUT std_logic
);
END COMPONENT;

SIGNAL sdin : std_logic:= '0';
SIGNAL sdout : std_logic:= '0';
SIGNAL dsdin : std_logic:= '0';
SIGNAL dsdout : std_logic:= '0';

--Generate data to test
signal data : std_logic_vector(63 downto 0);
signal clk : std_logic:= '0';
SIGNAL reset : std_logic:= '1';
SIGNAL notclk : std_logic;

BEGIN

reset <= '0' after 180 ns;
clk <= not clk after 50 ns; -- about 8448K (E2)
notclk <= not clk;

PROCESS (clk)
begin
if reset = '1' then
data <= "1111111011011100101110101001100001110110010101000011001000010000";
elsif clk'event and clk = '1' then
data <= data(62 downto 0) & data(63) ;
end if ;
end process ;
sdin <= data(63);

uscram: scrambler PORT MAP(
reset => reset,
datain => sdin,
clock => notclk,
dataout => sdout
);

dsdin <= sdout;
udscram: descram PORT MAP(
reset => reset,
datain => dsdin,
clock => clk,
dataout => dsdout
);

END;

 

[Blowfishie]

scrambler.vhd

The reason that it's not descrambling properly is that the value in the descrambler's shift-register is 1 clock cycle ahead of the scrambler's one. Effectively the descrambler is descrambling at the wrong point in time.

You should try to introduce some method of synchronisation between the scrambler and descrambler. The SONET/SDH method of this is to introduce a regular start of frame pattern that is not scrambled (F6F6F6282828), while the rest of the frame is scrambled. The scrambler resets its shift-register contents while these bytes are being sent. The descrambler's is reset by a frame-detection module during this time.

To get your test case code to work, you can introduce a 1 cycle delay in the bit that is used to descramble like this:

architecture behaviour of descram is
  signal shift_reg : std_logic_vector(6 downto 0);  -- shift register
  signal tmp_delay : std_logic; -- Blowfshie's 1 cycle delay
begin
  process(reset, clock, datain)
  begin
    if reset = '1' then
      shift_reg <= (others => '1');
      tmp_delay <= '0';
      dataout	<= datain;
    elsif (clock'event and clock = '1') then
      shift_reg <= shift_reg(5 downto 0) & datain;

      tmp_delay <= shift_reg(6) xor shift_reg(3);

      dataout <= datain xor tmp_delay;
    end if;
  end process;
end behaviour;

Note: My implementation of the shift register is the same as yours, it is just a bit more compact.

Another note: This only works because I've manually corrected the delay under simulation. In a real system, you will need to find a way to guarantee the relationship between the data and the scrambler/descrambler shift-register contents.