I have done similar module before, input 2024 bits data and get 24 bits crc check sum.
I designed a state machine with s0, s1, s2 phase, s0 is the initial phase and reset everything; s1 do the check sum calculation and ouput the original data; s2 do the check sum output.
when in s1, the register is enabled, thus the check sum keeps changing
when it comes to s2, the register is not enabled and thus hold the final check sum.
then you can use mux to output the check sum as you wish.
hope this might help...