About the second question:
You need multiple output sources because there's many devices that operate with different voltage levels...some work with 3.3V, some with 2.5V, 1.8V etc...
thanks for your reply,
In 1st question -
There is a Spartan6 SelectIO resource guide in xilinx website.
there are single ended pins and differential I/O pins like LVCOMS, TMDS, and many more, I want to know that why do we need them, what are their significance, and how exactly are they implemented.
The answer to this question is similar to the answer of the second question.
An FPGA is is built from the ground up as a very flexible device. It has many buffer types at its IOs to be able to communicate in the required protocol.
Some protocols require differential lines (LVDS), some require very high speed serial interfaces (PCIe multi gigabit tx/rx), some lines use low voltage levels to save power (1.2V) while others "speak louder" (3.3V). Some, high speed signals require very fast slew rates (rise times) while others require lower slew rates for better signal integrity...The need for different IO types comes from engineering needs - FPGA manufacturers address those needs with very flexible and integrated devices.
Can you please send by any link , where the implementation of such IO is demonstrated, I mean the syntax of using this attribute, I believe that this is done in edit UCF, please correct me if I am wrong.
I don't have a reay example - I suggest you create a new project and using the PlanAhead tool create a UCF file.
Edit the buffer options to different values using the GUI and save the UCF file.
Afterwards, if you open the file you'll see the changes.