Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Selecting different include files in verilog

Status
Not open for further replies.

shakti_pattnaik

Newbie level 5
Joined
Apr 28, 2006
Messages
8
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Location
Bangalore
Activity points
1,349
verilog include

Few queries:
1) I've 3 different INCLUDE files and 3 different TASKS, one particular task maps to one particular include file. How can be select the tasks with their respective include files in one verilog file.

2) Can the include file be defined inside a task so that once we call the task the include file also gets called.
 

thiagu_comp

Member level 1
Joined
Jun 5, 2009
Messages
37
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
Bangalore
Activity points
1,502
include verilog

1 --> There is no need to refer to which include file has the specific task. If the file containing the task in included before calling the task, that is enough.
2 --> It depends on what is written inside the file which is included. Syntactically, it is not wrong.
 
Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top