Segmented DAC design urgent

[vsvamsi]

I have a montonicity issue with my DAC with worst case DNL during transition from 0111 1111 to 1000 000. There is a massive glitch during this transition. the output impedance of current source I designed is very high 10Mohms. I have noticed the glitches in certain bits from the D flip flop outputs which inputs the signal to the switches of the current source. I have tested the thermometer decoder,It is working great.
Can u tell me what i should do to rectify this error. I have been working on it for long time.

 

[BradtheRad]

transition from 0111 1111 to 1000 000

This means many switches turn off a lesser current, and one switch turns on a greater current.
A glitch can occur if any of the switches are not in sync.

Have you tried installing a capacitor at the output, in order to soften the transitions?
Since you state an output impedance of 10 M, the capacitor value can be very small. There must be some amount of input series resistance, in order for the capacitor to do its job.

This shows the general concept in its simplest form (whereas your circuit is more complex of course).

 

[vsvamsi]

Adding capacitance...would slow done my dac...which I believe is a bad idea....is there any solution ...should I develop any particular logic for these combinations 1000 000 and 0111 1111 to assert the current sources...

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Is it common for these glitches to occur ??? ....I would also like to add that I have to use a cap in my load...so perhaps it could filter out that glitch

 

[BradtheRad]

1.

You may be able to tailor the capacitor value to be small enough, so that the time constant is so short that the analog output settles quickly, before the next digital value comes along.

2.

There are a few methods of DAC. You might get better sync if you use a different method. Or perhaps a different binary switching circuit.