second counter complete vhdl

[andrea080690]

Hi, I'm a principiant about VHDL and I'm doing a second counter up and down, with asincron reset, whit possibility to set a final value if is counting up and a start value if is counting down. I put also a minutes counter but it is not required. I did the rtl test and all was work, but on the timing test, outs are ever "00000". How can I solve it? I think I udes a lot of elsif.

-- dichiarazione librerie
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.ALL;
use IEEE.std_logic_unsigned.ALL;

-- dichiarazione entità --
entity contatore is

port (clk: IN std_logic;
rst: IN std_logic;
inizio: IN std_logic_vector (0 to 5);
fine: IN std_logic_vector (0 to 5);
updown: IN std_logic;
Z: OUT std_logic_vector (0 to 5);
X: OUT std_logic_vector (0 to 3));
end contatore;

-- dichiarazione architettura comportamentale--

architecture comportamentale of contatore is
  signal cont: std_logic_vector (0 to 5);
  signal min: std_logic_vector (0 to 3);
  signal egual1, egual2: std_logic;
  
  begin
    process (clk, rst, inizio, fine, updown)
	   begin 	
		
		
		if(cont = fine and updown= '1') then  -- imposto il segnale egual1 a 1 se il cont=fine e sto contando in avanti
			egual1 <= '1';
		else
			egual1 <= '0';
		end if;
		
		if(cont = "000000" and updown= '0') then  -- imposto il segnale egual2 a 1 se il cont=0 e sto contando in dietro
			egual2 <= '1';
		else
			egual2 <= '0';
		end if;
		
		
		  if (rst='1') then
		  cont <= (others => '0' );
		  min <= (others => '0' );
		  elsif ( min= "1010") then
		  min <= (others => '0' );
		  
		  elsif (updown= '1' and egual1='1') then
		  cont <= "000000";
		  elsif (updown= '0' and egual2='1') then
		  cont <= inizio;
		  
		   elsif (clk'EVENT and clk='1' and updown= '1' and cont="111011") then -- se updown=1 sommo
	      cont <= (others => '0' );
			min<= min +'1';
			elsif (clk'EVENT and clk='1' and updown= '1') then -- se updown=1 sommo
	      cont <= cont + '1';
			elsif (clk'EVENT and clk='1' and updown= '0') then -- se updown=0 sottraggo
			cont <= cont - '1';
			
	 	  end if;
		 		  
		 end process;
		 Z<= cont;
		 x<= min;
	end comportamentale;

 

[barry]

I didn't really look that closely at your code, but I can tell you that you're going to have to restructure it. You should have one AND ONLY ONE clk'event statement in the process. You should put all the other conditions inside the "if clk'event" block.

 

[ads-ee]

besides what barry said, that ONE AND ONLY ONE clk'event statement should be right after the process statement or following an asynchronous reset statement. Right now you have them embedded inside a nested asynchronous blob of code.