I am not an expert in SDRAM, but as far as I know, the refresh cycles is determined by the internal structure of Bank/Row, and it is not always 4096, like the one I am using now, IS42S32160F, it needs 8192 cycles every 64mS.
There is an internal refresh address generator which generates the refresh address by itself, you don't have to care about it. What you have to do is just issuing refresh command 4096 times every 64mS (can be any pattern, does not have to be evenly distributed, can be even refresh in a burst fashion), the SDRAM itself will take care of the rest.