SDRAM memory controller design (testing in xilinx ise)

shrikanthke · Sep 1, 2012

i have a verilog code for memory .I want to check read and write operation in it . i gave address and data. but i want to load memory register in it (before read and write ). probelem is mode reg is declared as register (not as any input or output).so in what form i shud give it in testbench. i cant directly give its value since it is not a input or a output. i think it shud be given something as "force.........."
help me on this pls.

HUANGWEI · Feb 21, 2013

hello, I'm doing something about the SDRAM which controled by XILINX, but I haven't know regard to the SDRAM. I research something about SDRAM to you, so can you send some resource to me of SDRAM or reference code to help me complete my program. I'm great to wait your repeating.

SDRAM memory controller design (testing in xilinx ise)

shrikanthke

Newbie level 5

HUANGWEI

Newbie level 1

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SDRAM memory controller design (testing in xilinx ise)

shrikanthke

Newbie level 5

HUANGWEI

Newbie level 1

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