SDRAM Interfacing with FPGA

hi guys,
i want to interface SDRAM IS42S16160B with vertix 5 FPGA. we want to write data on SDRAM and then read it back, but we are facing some problem. Here is a part of code which we have written.
we need some help. Regards
Talha

INIT: begin
#(33000*full_clk) nop (0, hi_z); // Nop
precharge_all_bank(0, hi_z); // Precharge ALL Bank
//nop (0, hi_z); // Nop
#(8*full_clk) auto_refresh; // Auto Refresh
nop (0, hi_z); // Nop
load_mode_reg (55); // Load Mode: Lat = 1, BL = 4, Seq
nop (0, hi_z);
active (0, cntr_row, hi_z); // Active: Bank = 0, Row = 0 // Nop
nop (0, hi_z); // Nop
NEXT_STATE = WRITE;
end

WRITE: begin
if (cntr_main == 100)
begin
nop(0, memory[cntr_main]);

//precharge_all_bank(0, hi_z);
burst_term;
cntr_col = 0;
cntr_row = 0;
cntr_main = 0;
active(0,cntr_row,hi_z);
//$stop;
NEXT_STATE = READ;
end
else
if (cntr_col == 0 || cntr_col == 255)
begin
if (cntr_col == 255)begin
cntr_col = 0;
cntr_row = cntr_row +1;
precharge_all_bank(0, hi_z); // Precharge ALL Bank
nop (0, hi_z); // Nop
active (0, cntr_row, hi_z); // Active: Bank = 0, Row = 0
nop (0, hi_z); // Nop
nop (0, hi_z);end // Nop
else begin
cntr_col = cntr_col + 1;
cntr_row = cntr_row;end
write (0, cntr_col, memory[cntr_main],0);
nop (0, memory[cntr_main]); // Nop
//cntr_col = cntr_col + 1;
cntr_main = cntr_main + 1;
NEXT_STATE = WRITE;
end
else
begin
nop(0, memory[cntr_main]);
cntr_main = cntr_main + 1;
cntr_col = cntr_col + 1;
NEXT_STATE = WRITE;
end
end