SPEF file provides capacitance and resistance only, but signoff sdf is generated using some tool specific algorithms bases on SPEF and other factors like loading, PVT, etc. SDF contains delay values, SPEF contaings resistance and capacitance values. Pre layout , only SDF files are used for timing analysis, which are calculated again using .lib files where timing information for standard cells are present as well as wire load model. Post layout, RC is extracted and more realistic interconnect delays can be calculated based on SPEF file. These delays will be reflected in signoff SDF when SPEF files are used.