sdf annotate asynchronous paths in a multi-clock design

[tariq786]

How to sdf back-annotate asynchronous paths in a multi-clock design

Hi friends

I want to know how can i SDF annotate only clock domain crossings (CDC) in a gate-level netlist during gate-level "timing" simulation?
SDF file contains all the gate and interconnect delays of cells in a synthesized netlist. How to make sure that i do SDF back-annotation of only CDC paths and nothing else in your design? The reason for doing this is that you want to speedup gate-level simulation by selective SDF back-annotation rather than full SDF annotation.

Please let me know if you are looking for more information. I am using cadence ncverilog simulator for gate-level simulation

Thanks

Kind Regards,
tariq786

 

[paulki]

Re: How to sdf back-annotate asynchronous paths in a multi-clock design

If you are doing only CDC path to get SDF annotate, and not considering the other part in GLS then you may get functional failures itself due to timing issues. These functional FAILURE would not actual failure itself. This is not advisable even though faster GLS runs.

You can hack the SDF file to create only CDC paths to get annotate and others put "0" by some perl script.

Thanks,
Paul

 

[tariq786]

Thanks Paulki

but here is another way using Cadence NC-Verilog simulator


-tfile <my_tfile_name>

this timing file holds the path to the first sync register and disables all the timing behaviour and all checks. your can also disable timing only (see cadence documentation). One example line looks like this:
PATH :top.module1.module2.module3.first_sync_reg -timing


Original post is here

https://www.cadence.com/Community/forums/t/20405.aspx