am85
Member level 2
Hi,
I am using a Spartan 6 FPGA. I am reading from an ADC (18 bit 1 MHz) and I want to process the data on the FPGA then write it to an external SD Memory card at a rate of 10 MB/s to 20 MB/s (the ADC data + the results). I wanted to use a core from Xilinx to facilitate the interface implementation and not to have to write it all by myself. The SATA interface (using Spartan 6 GTP transceiver wizard) would provide a high data rate but then i will need to buy a more expensive FPGA with embedded transceivers and the interface is complicated and will consume high resources utilization. On the other hand SPI might be too slow. Does anyone know what is the maximum data rate (read and write) I can achieve with Xilinx SPI core to SD Memory? How can I overcome the SPI bottleneck? Are there any other interfaces available as xilinx cores i can use to interface the SD Memory?
Thanks a lot.
I am using a Spartan 6 FPGA. I am reading from an ADC (18 bit 1 MHz) and I want to process the data on the FPGA then write it to an external SD Memory card at a rate of 10 MB/s to 20 MB/s (the ADC data + the results). I wanted to use a core from Xilinx to facilitate the interface implementation and not to have to write it all by myself. The SATA interface (using Spartan 6 GTP transceiver wizard) would provide a high data rate but then i will need to buy a more expensive FPGA with embedded transceivers and the interface is complicated and will consume high resources utilization. On the other hand SPI might be too slow. Does anyone know what is the maximum data rate (read and write) I can achieve with Xilinx SPI core to SD Memory? How can I overcome the SPI bottleneck? Are there any other interfaces available as xilinx cores i can use to interface the SD Memory?
Thanks a lot.
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