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Scrolling Text on 7 segment Display

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yttuncel

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BASYS2 Text Scrolling

Hello,

I am near to end in my project but stuck at some point. I can not resolve the problem

After deciding VHDL is having a hard time shifting indexes of arrays, I decided to change my shifter module. Now it is properly compiling and the RTL schematic seems true, but unfortunately I used a rather non-innovative way to shift the scancodes.

I defined an 64bit std_logic_vector that can hold up to 8 scancodes, and then parsed the 4 MSBmost bytes of this vector, and directed them to seven segment controller, that muxes the inputs and decides which seven segment will be enabled. I am thinking that I have problems with clock, but seeing nothing on the display makes me think some part of the device is malfunctioning. I am sure my keyboard controller works fine, as I tried it outindividually, shifter looks fine as well( I also tried this one on FPGA but without slowing the clock down, but nevertheless I was able to see the last scancode I entered), I haven't thought of any way/method to try out 7 segment controller, but that seems fine too. I don't know what the problem is :(

top.JPG

Shifter.vhd

Code VHDL - [expand]
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library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use IEEE.numeric_std.all;
    
    entity my_shifter is
            port(clk      : in  std_logic;
                    Scan_Dav : in  std_logic;
                    Data_in  : in  std_logic_vector (7 downto 0);
                    O1 : out std_logic_vector(7 downto 0);
                    O2 : out std_logic_vector(7 downto 0);
                    O3 : out std_logic_vector(7 downto 0);
                    O4 : out std_logic_vector(7 downto 0)
                    );
    end my_shifter;
    
    architecture bhv of my_shifter is
    
    signal bytes : std_logic_vector(63 downto 0);
    begin
        process (clk) begin
            if rising_edge(clk) then
                    --if Scan_Dav = '1' then
                        bytes <= bytes (bytes'high-8 downto 0) & Data_in;
                    --end if;
              end if;
        end process;
         O1 <= bytes(63 downto 56);
         O2 <= bytes(55 downto 48);
         O3 <= bytes(47 downto 40);
         O4 <= bytes(39 downto 32);
    end bhv;


clkdivide.vhd

Code VHDL - [expand]
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library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity clkdivide is
        Port (clkin: in std_logic;
                clkout:out std_logic );
    end clkdivide;
    
    architecture Behavioral of clkdivide is
        signal int_clock:std_logic;
        begin
            clkout<=int_clock;
        process(clkin)
            variable var:integer range 0 to 12500 :=0;
            begin
                if (clkin'event and clkin = '1') then
                    if var = 12500 then
                        int_clock <= not int_clock; 
                        var:=0;
                    else 
                        var:=var+1;
                    end if;
                end if;
        end process;
    end Behavioral;


SevenSegmentControl.vhd:

Code VHDL - [expand]
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library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    
    entity SevenSegmentController is
        port (
            CLK: in std_logic;
            DEC1, DEC2, DEC3, DEC4: in std_logic_vector(7 downto 0);
            SEGMENTS: out std_logic_vector(6 downto 0);
            ANODES: out std_logic_vector(3 downto 0)
        );
    end SevenSegmentController;
    
    architecture Behavioral of SevenSegmentController is
       signal DecoderInput: std_logic_vector(7 downto 0);
        signal CurrentDisplay: std_logic_vector(1 downto 0) := "00";
        signal Prescaler: std_logic_vector(15 downto 0) := (others => '0');
    begin
    
        Multiplex: process(CLK)
        begin
            if rising_edge(CLK) then
                if Prescaler(15) = '0' then
                    Prescaler <= Prescaler + 1;
                else
                    CurrentDisplay <= CurrentDisplay + 1;
                    Prescaler <= (others => '0');
                end if;
            end if;
        end process Multiplex;
    
        SevenSegmentDecoder: entity work.SevenSegment_Decoder(Behavioral)
            generic map ( INVERT_OUTPUT => '1' )
            port map ( number => DecoderInput, segment => SEGMENTS );   
            
        DecoderInput <= DEC1 when CurrentDisplay = "00" else
                            DEC2 when CurrentDisplay = "01" else
                             DEC3 when CurrentDisplay = "10" else
                             DEC4 when CurrentDisplay = "11";
                             
       ANODES <= "0111" when CurrentDisplay = "00" else
                     "1011" when CurrentDisplay = "01" else
                     "1101" when CurrentDisplay = "10" else
                     "1110" when CurrentDisplay = "11";              
    
    end Behavioral;



Text is not scrolling.
Any help is greatly appreciated.

EDIT: By adjusting clocks (I changed Keyboard Controller's clock input and changed the divider output as well) I managed to read text on seven segment display. However it is buggy. When I press P and O, I read "PPPOO..". Any suggestions?
 
Last edited:

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