The Nmos and Pmos are the Pull-Down and the Pull-Up af a CMOS inverter. If the control signal is low, the pmos is on, and the DC/DC input power voltage is 3V. If the control signal is high the nmos is on and the DC/DC input power voltage is connected to ground through the resistors.
I try to guess the situation: charge pumps multiply the amplitude of a clock signal and they can add (or not) a voltage as input (which adds to the output). So maybe this circuit adds (or not) the input initial voltage.
Use of Schottky diodes is preferable in charge pump circuits because their threshold voltage [tex:178e22369f]V_{\gamma}[/tex:178e22369f] is sensibly lower. Consider that [tex:178e22369f]V_{\gamma}[/tex:178e22369f] affects the voltage pumping gain of the charge pump: the output voltage of such a circuit is
I think maybe this nomenclature refers to a synchronous "reset switch" in a
buck converter; an NMOS low side switch can recirculate the inductor current
with lower conduction losses (up to the point that Rds(on)*Iinductor exceeds
the Schottky Vf for the same current). The cost is the gate charge of the
low side switch, which goes to switching losses instead. The cheap way is a
Schottky and this design is "Schottky-free".
Schottky forward losses loom larger, as the output voltage goes lower; your
efficiency cannot exceed (Vout-Vf)/Vout. Or something close to that.
Sounds reasonable. Unfortunately, a charge pump uses no inductor and can't work without push-pull synchronous switches at the driver side, as far as I see. So related to the presented circuit and particularly the control signal, the term seems completely meaningless.