SCHEMATICS AND VHDL....!!GUIDANCE NEEDED...

[Mirzaaur]

dear all,

I tried to convert this schamtics into VHDL code. with schmatics simulation it works fine. but VHDL code it gives wrong result in simulation.

can any one check if schematics and vhdl code are equilent ???

thanks in advance,

mirza


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a is
Port (
siu_br : in STD_LOGIC;
siu_bi : in STD_LOGIC;
dcs_br : in STD_LOGIC;
dcs_bi : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
siu_bg : out STD_LOGIC;
dcs_bg : out STD_LOGIC);
end a;

architecture A_A of a is
signal sr_d : std_logic;
signal sr_and_diinv : std_logic;
signal dr_and_siinv : std_logic;
signal sg_r : std_logic;
signal dg_r : std_logic;
begin
siu_bg <= sg_r;
dcs_bg <= dg_r;

process(siu_br,dcs_br)
begin
if dcs_br='0' then
sr_d <= siu_br;
end if;
end process;

sr_and_diinv <= sr_d and (not dcs_bi);
process(clk,rst)
begin
if rst='1' then
sg_r <= '0';
elsif clk' event and clk='1' then
if siu_bi='1' or dg_r='0' then
sg_r <= sr_and_diinv;
end if;
end if;
end process;


dr_and_siinv <= dcs_br and (not siu_bi);
process(clk,rst)
begin
if rst='1' then
dg_r <= '0';
elsif clk' event and clk='1' then
if dcs_bi='1' or sg_r='0' then
dg_r <= dr_and_siinv;
end if;
end if;
end process;

end A_A;


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[vlsi_whiz]

IF you could give the testbench or the simulated waveforms for the schematic it would help in solving this query.