Schematic view from verilog, without standard cells

[zoraide]

Hi,
I'm working with cadence, and I'd like to create a schematic view from a verilog file.
The circuit described in this verilog file, doesn't use standard cells....

How can i do?

thanks.

 

[dexter_ex_2ks]

Yes, but if I'm not wrong, first you must synthesis from RTL code to gate level. And try to save it as EDIF type. Probably there is a better solution, but I can't think of something else right now.

 

[zoraide]

Thank you dexter.

Do you know if there is this tool in cadence environment ?

 

[dexter_ex_2ks]

Well I think for synthesis (from Cadence) you can use BuildGates (bg_shell or pks_shell, you'll have the Ambit std_cells) or RTL Compiler (RC - I've never used this tool, I wish too ). And if you want, you can use DesignCompile (DC from Synopsys).

You can synthesis with Xilinx too (you can download Xilinx WebPack from their site, it is meant for study or trial purpose....I don't remember), make a project , place your RTL code... and after that you can synthesis...

Good luck, and please tell me how you resolved the problem

Have a nice day

 

[zoraide]

Ok, thank you very much dexter.

Have a nice day