I generally use it just for LVS, but in the Assura forms it
appears that you can select any two arbitrary netlist sources.
But I haven't tried your specific thing. In my environment
the verification tools are only spawned from layout windows,
so you might have to begin there. You could always check
one schematic against its layout, then a second against
the same "benchmark". Though this would require a layout
to begin with.
Some tools work using SPICE format netlists, which could
come from anywhere.