However, you've posted to the Analog Circuit Design and none of your previous posts said "digital". You'll get a better and quicker answer in the digital section of the EDAboard.
I am designing a frequency systhesizer.
This block has a divide by 3 (frequency divider) block.
I need a circuit with 50 % duty cycle.
Currently I am desiginig the other blocks.
So if some body can direclty give me some inputs on this issue it will be beneficial for me, as it will reduce the time for the project.
may i ask what's the frequency range it works at ? and how much current it draws.
i also used this architecture to realize a divider by 3, passed full corner simulation in a 0.18um CMOS process. but the current consumption is 6~10mA (it changes due to reference current is generated by internal resistor ) which is not acceptable。
so i am considering to change a method to realize divide by 3, first by 1.5, then by 2.
but not done yet, any idea?