pichuang
Newbie level 6
40nm performance gate delay
Hi,
I am working in 65nm technology and I have a problem with the post layout and schematic performance difference. Take an example of the conventional transmission gate based mux, the post layout simulation has a performance degradation of at least 30% over the schematic simulation. I am wondering if anyone else has the similar situation?
Thanks,
Hi,
I am working in 65nm technology and I have a problem with the post layout and schematic performance difference. Take an example of the conventional transmission gate based mux, the post layout simulation has a performance degradation of at least 30% over the schematic simulation. I am wondering if anyone else has the similar situation?
Thanks,