Scan optimization: is it during scan insertion or ....

[jayTudu]

Hi DFTian,

I am bit doubtful about the scan optimization ( constraint: power, area), exactly when it is done, is it during scan insertion that is done with DFTCompiler or it has to do with Astro (synopsys tool for scan optimization and ....). Please give your healthy reply.

Regards,
JaYN

 

[vlsichipdesigner]

hi,

my2cents,

it is done during Scan-phase in DFT compiler itself, as soon as you perform insert_dft command with your scan constraints.

myprayers,
chip designmade easy
https://www.vlsichipdesign.com

 

[jayTudu]

hi vcd,

thanks for responding me. I am still not convinced about the scan optimization done by DFT-compiler. During the compilation time or during dft insertion there is no information about the placement and routing, I mean there is no way to extract the geometrical information during scan insertion phase. If the placement information is not known then there is no any other parameter (area and clock) to optimize. And this assumption made me think about placement and routing phase as a proper phase for area and clock optimization.
I still do not have very detail and practical idea. I am just reading the Astro(tool for placement and routing synopsys) manual for having the idea about what is done during placement and routing.
I am working in the area of DFT scan design and low power test patter.

Thanks,
Jaynarayan

 

[vlsichipdesigner]

hi,

i like the way you think.

yes what ever best possible optimization is done at DFT compiler and scan order file is generated.
scan order file is given as input to the place and route tool, now based on other physical constraints as you mentioned are taken in to account, and tool does scan-reordering to meet the requirements.

myprayers,
chip design made easy
https://www.vlsichipdesign.com

 

[chyau]

Hi guy,

The scan optimization is doing in Astro.
You don't have any physical information(real rc value) how to do optimization.
Before CTS, you need to delete scan chain.
After CTS, you need to connect scan chain to do placement optimization.

Best Regards,
chyau

 

[raju3295]

hi,
scan stching is done according to the constraints given and DFT compiler will do to it best in meeting the constraints with the inputs it has, then upon this, pnr tool will do the reordering of the scan cells with in the scan chain,in particular, thy will try to maintain the partitions even.

hi chyau,,
Can u tell me plz,, why we need to delete the scan chain before CTS.

 

[jayTudu]

Hi frnd,
The discussion got interesting shape. I thank all of you for interesting discussion. I am just curious about the question asked by raju to chyu. I will be following the discussion.

Regards,
JaY

 

[cop02ia]

Hi,

Scan chain is disconnected before any change in placement so that the order of scan flip-flops will be optimal.
It is not just because it is done before CTS - it is because of he placement changes to be done (here, it is because placement optimization i.e. no placement optimization after CTS, then, no need for scan-chain to be deleted & re-connected).

Suppose you don't disconnect before placement changes. Once you do changes to the cell placement, you might have 1 scan FF at say, the far right of your design core while the next connection is to another scan FF at the left edge of your design core. And in between them are lots of other scan FFs which could have been used.

Now, routing like this can drive you nuts, right?
Simpler would be to route scan connections from the far right, then to the scan FFs in the middle, and later on to the scan FF on the left edge.

My 2 cents worth.

Best regards.

 

[chyau]

Hi raju,

I mean delete scan chain is only delete net ,not cell for scan reordering.
It can avoid scan net cross on chip to bring about routing resource not enougth.
Tool depend on scan cell placement to calculate accurary RC value to decreease buffer insertion.

Best Regards,
Chyau

 

[jayTudu]

Hi frnd I have one more small question.
The test pattern (transition fault) generated using the gate level netlist obtained just after scan synthesis and the pattern generated using the netlist obtained after astro will be same or they differ. I have not done any experiment yet.
Any experience answer will be helpful for me to finish my work quickly.
with Joy,
JaYTuDu

 

[sunilbudumuru]

Hello Jay,

However, your postlayout netlist will differ compared to the prelayout netlist due to adding of buffers during CTS, SC reordering etc..

So, do generate the patterns once again on the postlayout netlist

Regards,
Sunil Budumuru
www.asic-dft.com