BTW mrflibble, I did a clean project when I discovered the errors and it doesn't help.... I think the cores need to be removed then added again.To prevent any surprised you should first do a Clean project in ISE, and then do that Regenerate all cores again.
BTW mrflibble, I did a clean project when I discovered the errors and it doesn't help.... I think the cores need to be removed then added again.
I have actually tried all alternatives available. Even if i delete and recreate the cores, it doesn't seem to work. However I shall try once more to delete the ipcore directory that comes with this program and recreate it. The program was probably created with ISE 12 version. I have ISE 14.6
As to instructions on how to do "this", read Xilinx's documentation. I'm certainly not going to "read it to you".is it possible that i just create a new project. while using the source codes from univ of massachusettes.I will add my own ip cores and other files. Please instruct me on how to do this?
It was probably created with ISE 14.2, as determined during my cornflakes because I was curious.
And the original for V6 from which it was derived, no idea what version ISE that was.
Sounds like a decent plan to try. Especially since you mention your target is virtex-6 .. oh wait, wrong university. See, I should not assume things. Reread that page you linked to again. Then you see the other uni being mentioned, and the original design on opencores that is for v6. As for instructions, I am of the school of thought that you first try it yourself several times, fail a few times, try again and only after that you ask. ;-)
Well, I got it to work. Bitfile and all. But the design as distributed in that .zip doesn't work right out of the box. And after getting it to work I took a look at the webpage again, and nope, the required steps to get it to work are not described there.
Amusing detail is that the design as is doesn't even fit the target board.But if you take sata_core as the top level then you find that this does fit. Then of course the constraints in the ucf are wrong, but that's not a big deal since you can fix the signal names. Or do what I did (being lazy and all that), keep the sata_test wrapper. That way you can keep the same signal names in the ucf. And then just remove the ICON + ILA from that top level. They look like they were plonked in as an afterthought anyways.
Anyways, this was a nice example on how not to distribute work. And a fun exercise of the troubleshooting skills.
In closing, if virtex-6 is your intended target, I would use the original design from opencores.
From that webpage you linked to:
This design is based on a SATA core created at the University of North Carolina at Charlotte for Virtex-6 devices, created by Ron Sass, Ashwin Mendon, and Bin Huang. That design is available here. Some new features have been added in this version, including a replay buffer to improve reliability and new debugging modules.
https://opencores.org/project,sata_controller_core
That's the potentially less fscked up version for V6.
PS: Oh yeah, I used ISE 14.2 since that is what the project in the .zip used. Reduces the amount of surprises.
I agree that porting the backport to the original platform is a tad silly. :grin: The only reason I'd usually consider something like that is if the backport really is more like a fork, and the fork had useful additions, bug fixes, etc. But hey, you can always hope to learn something from said backport, and then carry that over to the original. In this case the backport had a few counter-examples on distribution. This one looks like zip it, ship it, and definitely do NOT test it.This is ridiculous if the design was originally a V6 and was back ported to a V4, but they want to port it from a V4 to a V6!?...
I was curious. Plus I like learning from other people's mistakes. Most of the time was actually spent reading other stuff, while waiting for regenerate cores to finish. That really is excruciatingly slow. My PC is not from 2014, but it's not exactly slow either. What of course doesn't help is that xilinx in their infinite wisdom has decided that firing a "regenerate all cores" cannot be run within multiple threads. So we have 1 core with 100% utilization, and the rest is just idling. Yes, well done! I like my software to behave like software from the previous millenium.Wow, you went to an awful lot of trouble...
*bookmark*I noticed that this student project version isn't the only SATA core on opencores. Another V6 version, which looks to be a project by either a working engineer/consultant or a knowledgeable hobbyist with a lot of experience. Plus I like the fact they have an AXI version available.
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