Actually, the TI link describes the traditional approach in building integrated SAR ADC with charge redistribution. The ADI link is a bit fuzzy to me since it doesn't even give an idea what is inside the DAC block.
Anyway, the comparator output is digital and it goes to the SAR logic. Everything happens internally. Basically, you sample the input on all CDAC caps. Then, the SAR logic starts reconfiguring the CDAC caps such that the comparator test for each bit of the ADC output. Based on your last figure, if the comparator says 1 it means Vin is bigger than the binary portion of Vref that it is being currently compared against. In this case the capacitor connected to Vref stays and the next LSB capacitor is connected also to Vref. Follows new comparison. If the comparator says 0, then the presently connected to Vref capacitor is disconnected from Vref and connected to gnd. The next LSB capacitor is connected to Vref and a new comparison follows. This procedure repeats until all capacitors in the CDAC are tested.
The configuration in the second figure differs from the one in the 3rd. In the second figure you sample Vin on a dedicated T/H and the DAC output is compared to that. At the end of the conversion the DAC output is within +/- 0.5*LSB from the sampled Vin.
In the 3rd figure, as I mentioned Vin is sampled on the CDAC itself and during the bit tests CDAC output is equal to a*Vref-Vin, where "a" can be 1/2, 3/4 or 1/4, 1/8 or 3/8 or 5/8 or 7/8, etc. depending on the path the binary search algorithm takes. At the end of the conversion CDAC output is within 0.5LSB away from 0V.