Sar adc _ using sample and hold block in sar adc and keep tranking with input signal

Hi everyone,
I am confusing how would I sample and hold the input signal in my SAR ADC and keep the tracking property between the input and output at the same time, I understand that either sampling the input and hold it for 6 clk cycles (in case of 6 bits) until the digital output appears or keep tracking the continuously changing input signal in each clk cycle??
Can anyone help?

akkafrawy said:

... sampling the input and hold it for 6 clk cycles (in case of 6 bits) until the digital output appears

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That's correct!

akkafrawy said:

Hi everyone,
I am confusing how would I sample and hold the input signal in my SAR ADC and keep the tracking property between the input and output at the same time, I understand that either sampling the input and hold it for 6 clk cycles (in case of 6 bits) until the digital output appears or keep tracking the continuously changing input signal in each clk cycle??
Can anyone help?

Click to expand...

nope, you should sample your signal each 6 cycle ( in case of 6 bit) in other world, you have two clock in your system , one for sampling and other for the SAR block ( Fsar=Fs&h/6) so, you should sample your input each 6 cycles of the internal clk ( SAR clock) and hold it during the conversion mode, so you have a new sample in the sample mode (after 6 cycles) and a hold state during the conversion mode , and so on
i wish i could help you