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Sampling Phase Detector baseband techniques (HELP)

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Nov 8, 2001
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sampling phase detector

Has anyone out there done any SPD designs. I can do the RF work no problem. Does anyone have any schematics for the opamp/baseband locking of the oscillator. I really need schematics or a good paper or description of how to configure the opamps.

Thanks in Advance


phase detector

I've done some work with a SPD at X-band frequencies.
The base band part is a standard PLL circuit, so there's no SPD specific work to do except the Null circuit (zero offset adjust) of the loop voltage.
After a simple RC-lowpass at the base-band output to reject the beat frequency you can amplify the loop voltage and use a opamp as a 1st order lowpass loop filter which is sufficient in most cases. Configuration of the opamps depends on your oscillator (resonator Q, tuning voltage range), tuning frequency range, how fast the pll has to lock after a tuning step, phase noise considerations, etc.


op amp phase detector

Thanks for the reply.
Do you have any schematics for a typical baseband opamp/filter setup. I can understand how the beat is done, and the offset but how does the loop distinguish between a frequency that is higher or lower than the actual lock frequency.
I would be grateful for a circuit diagram.

I should have explained this a little better.
Okay from the start.
The SPD will produce a beat frequency that is proportional to the frequency differenence betweem the multiplied refererence and the VCO.
(X and Ka will be the frequency, fixed LO, narrow bandwith, thus high Q from VTDRO)
Now if the two frequencies co-incide the beat frequency will be zero. If the frequency of the reference is lower than the VCO by say 1Mhz then the same frequency beat will be seen as if the signal frequency 1Mhz higher. (Please tell me if this is incorrect).
You now give this beat an offset of say VCC/2 and null it :?:
I guess this is so you can set the frequency of lock to vcc/2 to maximise the sweep range.
This is where i become confused. I just cannot picture how the loop can differentiate between the higher or lower frequency and thus be able to adjust the loop voltage. IE push the loop higher (>VCC/2) or pull it lower (<VCC/2).
I have seen a paper on a sweep generator and aquisition circuit to sweep the VCO and at the point of lock the loop stops the sweep generator and thus lock is acheived, but again i cannot see how it can adjust the loop if the frequency is shifted.
If you can clarify how this process works i would be grateful.


Bagster :wink:

sampling phase lock loop

you are right a phase detector can not differentiate between higher or lower frequency (that would be the job of a frequency detector) it gives you just the absolut beat frequency value without a sign; and still the locked loop will work, because it compares phase.

Let me try to explain from a static pint of view:
The phase detector compares the two input signals. If both input signals have the same frequency AND are in phase then the phase detector output will be zero (forgetting any offsets fot the moment). If both signals have the same frequency but there is a phase difference betweeen the two, the phase detector will deliver a constant voltage at the output.
The more phase difference, the more voltage you will get.
For example the voltage will be positive, if the phase of the dro minus the phase of the reference signal >0, and negative if the phase of the dro minus the phase of the reference signal <0.
So if the loop was locked, it will stay locked unless dro frequency is changing faster than your loop time constant allows or you leave your dro tuning range due to drift, etc.
The problem is how to get the loop locked.
If the loop is fast (high loop bandwith) and the frequency difference between the dro and the reference is not very much the spd delivers a beat frequency that modulates (sweeps) the dro until it locks automatically.
The other possibility is the sweep circuit you mentioned. I think one is described in

Puglia, K.V. “Phase-Locked DRO Uses a Sampling Phase Detector”, Microwaves & RF, July 1993

Hope that could help a bit,


Thanks, i get it now. Can you talk me through the analogue circuitry......
IE the offset and the low pass filter.
Firstly, you filter the signal to remove the beat, then you do you add an offset to get the loop (when in lock) voltage to vcc/2, is this correct. OR do you offset the voltage (null it to Vcc/2) with the beat note then filter it and pass it through the loop filter?
I can do the loop filter, so this is no problem.
I really appreciate the help.

Bagster :wink:

spd pll circuit

1st filter the beat (1st order RC-LP)
2nd get your loo bandwith IE 10kHz LP with op-amp
3rd aquisition circuit (which is half as difficult as it seems to be)
4th the offset is IE easily added to the aquisition circuit

Attached you find a good article with some formulas to design the right op-amp circuitry. There is also a part about estimating the phase noise you will get for the whole system.


please help find phase detector diagram

I am currently designing a PLL at 2 GHz using SPLD. Has anyone done temperature cycling of the cricuit and PLL is able to track the VCO or DRO temperature variations ? Regarding the sweep cricuit, I am using a wein-bridge oscillator and biasing it to the desired voltage level. But I found the amplitude of the oscillator is not stable. Can anyone help me on this ? Also, How much power level you re feeding to SPLD. Currently, I am using 23 dBm , which I found very high..any idea for reducing the power requirement.

sampling phase detector theory

Hi Bagster, Can you upload this paper "Phase-Locked DRO Uses a Sampling Phase Detector" ? I need it , thanks in advance

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