I assume that the circuit on the right side is intended to work as a kind of active current mirror. To understand the non-ideal behaviour, you would want to look at individual branch currents and node voltages.
You didn't mention what causes the rather high leakage currents in your MOSFETs. Thus I can't determine, if a compensation should work.
I don't know what an ideal simulator is. An ideal MOSFET model (simplified quadratic equation, SPICE Level 1) has Id = 0 for Vgs < Vth. A more realistic MOSFET model also implements a subtreshold region.
In my view, a simulator that doesn't provide devices with known model parameters and doesn't allow to modify it is useless for this kind of simulations.
- op amps have no drift or offset
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- IIRC the open loop gain of the op amps is 100000
I don't doubt, that this basic level device models will serve their purpose e.g. to visualize circuit operation. For the present problem, they obviously bring up issues that e.g. a standard single MOSFET ord complementary CMOS analog switch doesn't have.
In this case I would prefer a simple behavioral switch for the simulation, instead of designing complex compensation circuits, only needed to fix a simulator problem.
You didn't mention what causes the rather high leakage currents in your MOSFETs. Thus I can't determine, if a compensation should work.
It's very difficult (if not impossible) to build an analog sample and hold with <0.1mv acquisition and hold accuracy from a 12V signal for 10 minutes.
I would suggest you use a digital approach. Convert the signal with an A/D converter to a digital value and then output the digital value with a D/A. That can give you the accuracy you need with an infinite hold time. Of course 0.1mV out of 12V requires over 16-bit accuracy, so this solution is not trivial to implement either, but I think it's the only one that has a reasonable chance of success. ;-)
Out of curiosity why do you need such high accuracy?
So you say, that you are using the Falstad simulator to evaluate a compensation circuit, that is intended to work with real MOSFETs, and leakage currents smaller by 2 or 3 orders of magnitude? That hasn't been quite obvious... (The respective comments in post #3 have been added after my latest post)
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In a simulation that doesn't add artificial parameter tolerances and uses identical transistor exemplars, a "perfect" compensation should be possible. To trace the problems in the Falstad simulation, you need to know exact model parameters and look at voltages and currents, as suggested. I would try with a full featured SPICE simulator, e.g. LTSpice and real transistor models.
I am playing with sample+hold circuits in pspice and after getting frustrated with leakage currents across mosfet hold switch I went to falstad and tried to come up with a way to compensate for the leakage using ideal and identical components.
In a simulation that doesn't add artificial parameter tolerances and uses identical transistor exemplars, a "perfect" compensation should be possible. To trace the problems in the Falstad simulation, you need to know exact model parameters and look at voltages and currents, as suggested. I would try with a full featured SPICE simulator, e.g. LTSpice and real transistor models.
I've seen similar analog storage circuits in professional instruments designed in 60s or the latest in the 70s. Since that time, digital circuits as suggested by crutschow have taken their place.
The required 0.1 mV drop/600 s/1 µF translates to 0.16 pA total leakage (switch + capacitor + buffer), at least an ambitious specification.
A compensation circuit can be expected to reduce an unwanted quantity (e.g. BJT or JFET amplifier input current) by a considerable factor. My personal rule of thumb for similar compensation problems says: factor 5 is easy, factor 10 often possible, factor 20 hard to achieve. Of course it's about real circuits and measurement systems, not simulations. And the unwanted quantity must have a mostly systematical nature, which isn't clear for the MOSFET channel leakage.
Why is this happening? Am I missing some fundamental thing here? I don't quite understand what is going on that is causing the currents to be different despite all of the mosfet and resistor models being identical.
I guess these two statement contradict. The op-amp can only get the +/- inputs within .001% of each other (right?); I am having a hard time getting my head around how that .001% (e.g. 50uV @ 5V inputs) translates to leakage current offset though, I don't know if that could be the cause?
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