sample and hold, need your help!!

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welton

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Thank you in advance. I am designing a switch cap for sample and hold. I use transmission gates as switch and a cap to hold charge. The control signals to control PMOS and NMOS are C and CZ, then:
a) To avoid clock feedthrough, should the Tr/Tf of C/CZ be sharp or not? And is there any optimized Tr/Tf to avoid clock feedthrough?
b) What will be the effect if there is a skew between C and CZ when closing the switch?

Thanks for your help!!
 

I think if your transmission gate transistor sizes are large then their coupling capacitances (Cgs and Cgd) will be large so you need a slow transition in the clocks. If the sizes are small you can have a relatively faster transistion.
 

For the second part..you can try generating CZ from C (not the reverse)...such that after the holding capatior gets decouled from ip , it is connected for further processing....
 

Thank you all for your inputs.

Sankudey, I was confused because you mentioned about generating CZ from C but not reverse?? Could you please to explain more in more detail about part 2?

Also, I heard that the clock feedthrough effect can be simulated, but the channel charge injection can't be. Then, how much portion will the charge injection be if compared to clock feedthrough?
Thanks again!
 

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