kathalebm
Junior Member level 2
Hi All,
In my design I would like to sample analog signal whose frequency is 350 MHz using a 600KSPs ADC. In this case I thought of scaling down the frequency from 350 MHz to around 100KHz using a sample and hold circuit. Is my idea O.K or are there other techniques that I can use to scale down the frequency? If my idea is o.k, then can somebody propose me the SHA circuit required for this work. I have checked from the net but the ones I'm getting do not satisfy this requirement. Thanks in advance.
Kathale
In my design I would like to sample analog signal whose frequency is 350 MHz using a 600KSPs ADC. In this case I thought of scaling down the frequency from 350 MHz to around 100KHz using a sample and hold circuit. Is my idea O.K or are there other techniques that I can use to scale down the frequency? If my idea is o.k, then can somebody propose me the SHA circuit required for this work. I have checked from the net but the ones I'm getting do not satisfy this requirement. Thanks in advance.
Kathale
