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rx_eidleinfersel[2:0] signal of PHY IP Core for PCI Express(PIPE)

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trupesh.vasoya

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I am little confuse with description of rx_eidleinfersel[2:0] signal of PHY IP Core for PCI Express(PIPE), I want to use PHY IP core Megawizard function in my design but I am not sure about behavior of this input signal.
Clearly I'm not understanding exactly what this signal is telling me. Does anyone have some insight on this?
Thanks

User guide for PHY IP core :- www.altera.com/literature/ug/xcvr_user_guide.pdf
 

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