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Running for loop and stopping it in VHDL

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info_req

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Heloo dear,
I want to make cumulative histogram in VHDL. I am using for loop with wait ststement. It runs for ever. I need to run this for loop only once and then stop. Can any one tell me how it is possible.

Thanks
 

rsrinivas

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for loop

u have to put the for loop in an always block or a initial block according to verilog syntax which runs forever. so put a variable in the loop and check it before entering the loop.
this should work.
ex.
var=0;
if(var ==0)
begin
for()
var=1
end
end
regards
 

avimit

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Re: for loop

1. If you are doing a design, and are using a 'wait' statement in it. Its not going to synthesize.
2. Anyway... here is how u exit a vhdl loop.
use 'exit' thats it.

example:

process blah_blah:
variable index_var : integer ;
begin
index_var := 0;
for i in 0 to 10 loop
index_var := index_var+1;
-- do your loop things here
if(index_var = 1) then
exit;
end if;
end loop;
end process bhah_blah;
 

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