Rule_Violation_Explanation

[hot_snow]

Hello,

I have a 38mmx38mm PCB, my stack-up layer is like this: TOP/GND1/SIG1/SIG2/GND2/SIG3/PWR1/BOT.

I finished routing my board, now I try to make the partition of Power and GND. (It's the first time that I make a multilayer PCB)

I have 2 GND planes connected to GND net and I have 1 power plane. I splited this power plane to 3 power levels (1.2v, 1.8v and 3.3v), also I used polygon pours in signal midlayers.

The problem is : When I run "the Design rule check", I have more than 500 rule violations. In fact, I have 2 types of rule vioalations:

Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 277

Un-Routed Net Constraint ( (All) ) 223

Well, All the rule violations are like this:


Starved Thermal on GND1: Via (27.06mm,24.55mm) Top to Bottom
.
.
.
Starved Thermal on GND1: Via (22.26mm,26.15mm) Top to Bottom

Starved Thermal on GND2: Via (27.06mm,24.55mm) Top to Bottom
.
.
.
Starved Thermal on GND2: Via (22.26mm,26.15mm) Top to Bottom

Starved Thermal on InternalPlane1: Via (19.06mm,26.15mm) Top to Bottom
.
.
.
Starved Thermal on InternalPlane1: Via (16.2mm,8.63mm) Top to Bottom

//////////////////////////////////////////////////////////////////

Isolated copper: Split Plane (GND) on GND1. Copper island connected to pads/vias detected. Copper area is : 8,4 sq. mm
.
.
.
Isolated copper: Split Plane (GND) on GND1. Copper island connected to pads/vias detected. Copper area is : 0,055 sq. mm

Isolated copper: Split Plane (GND) on GND2. Copper island connected to pads/vias detected. Copper area is : 8,4 sq. mm
.
.
.
Isolated copper: Split Plane (GND) on GND2. Copper island connected to pads/vias detected. Copper area is : 0,055 sq. mm

Isolated copper: Split Plane (CVDD_CORE) on InternalPlane1. Copper island connected to pads/vias detected. Copper area is : 16 sq. mm
.
.
Isolated copper: Split Plane (DVDD_3V3) on InternalPlane1. Copper island connected to pads/vias detected. Copper area is : 1,9 sq. mm
.
.
Isolated copper: Split Plane (DVDD_1V8) on InternalPlane1. Copper island connected to pads/vias detected. Copper area is : 0,52 sq. mm

.
.


What means all these errors?

Any help will be appreciated.


Regards,

 

[kabaleevisu]

hi

i think clearance error please check design rules in net property (r u using pads right ??)

 

[hot_snow]

Sorry, I didn't understand you, well the clearance I have 2 rules: rule 1 is between (trace ,via and pads) is 0.1 mm.

The second is petween polygon pours and (trace,via pads) is 0.1 mm.


This is an image example of my board (the bright green color is the rule violation) :






Regards,

 

[keith1200rs]

There is too much on the image to be sure, but my guess is that your ground plane cannot connect to the vias. It is possible it also reports and error if it cannot use four spokes on a thermal - I don't know your software.

Keith

 

[hot_snow]

Well, I changed the clearance value of plane from 0.508 mm to 0.1mm also I changed the connect style from relief connect to direct connect, the number of violation rules decreased from 500 to 5. But I don't know if my board will work with a clearance value equal to 0.1 mm, also what's better to use: relief connect or direct connect?

In all case, now I tried to find a solution for the 5 violation errors.

 

[keith1200rs]

If you post the Gerbers & drill files it will be easier to see what the problem is.

Keith

 

[Anonymous_Ricky]

You can make direct contact for all vias you will not have any issue with that.
But via clearence is very low make sure you fabrication house can provide you that clearence.
You can reduce the width of your copper poured between the BGA Via and increase the clearence.(like if it is 0.2mm you can make it as 0.127mm).

 

[hot_snow]

Well,

First, I noticed that there are no clearance between the power plane and different net, what I have to do?

See image1:




Also, It stills 5 vioalation rules at my PCB design, I will show just one viaolation rule and could you tell me what's the problem (It's the first time that I make a power partition in a board).

Image2 (see the white arrow for the unrouted net):

the error message of this image is:

Un-Routed Net Constraint: Net DVDD_3V3 Between Pad F1-8 (8.977,21.634mm) And Track on layer Top (9.07,18.68mm)



Regards,

 

[cyberrat]

Try answering the question and letting others know what software you are using and they may be able to advise.

Has the plane got a clearance to other net pads set in the design rules of 0?

 

[hot_snow]

Well, I'm working with Altium Designer10.

No, the clearance that I set for the power plane is 0.127 mm and for the polygon pours is 0.127 mm

 

[Anonymous_Ricky]

As mentioned in error itself one of these pins is not getting connected to Net DVDD_3V3. do you have this net routed in any other layer also if so then check if a connection is made to these pins in that layer other wise try making one.

This no power isolation may be due to undefined signal to power plane, assign a net to it and check.

 

[hot_snow]

I have connected this net "DVDD_3V" only in the top and bottom layer, for the other pins this pins it's connected properly, so I'm wodering why it's not the same case of this 2 pins montioned in the image?

For the power plane, before this power plane was assigned to 1.8v net but when I splited it now I see that this power is assigned to "Multiple net".

 

[Anonymous_Ricky]

Check for proper connections then means it might be possible thast you have dran the trace but it is not connected properly.()but from image it doesnot look like getting connected check properly)

In power plane you need to check the settings then.

If you dont have any issue then upload the file for better look into the problems.