RTL VS nelist LEC problem, uing Candence tool

[yx.yang]

Hi, Friends:
I meet a problem when doing RTL VS netlist LEC check. The tool for synthesis is DC while using the Candence tool for LEC check.
The problem: DC indentify some DFFs with the same function, while LEC tool mis-located this, can causing copare fail.
For example:
input [1:0] sel;
reg [7:0] a;
reg [8:0] out;

alway @(posedge clk or negedge rstn)
if(!rstn)
a <= #1 8'h0;
else
case(sel[1:0])
2'h0: a <= #1 8'h0;
2'h1: a <= #1 8'h22;
2'h2: a <= #1 8'h44;
2'h3: a <= #1 8'h66;
endcase

alway @(posedge clk or negedge rstn)
if(!rstn) out <= #1 9'h0;
else out <= #1 a;

Form the RTL code, register a[3:0] and a[7:4] are function same, so DC may connect the DFF Q ouput of a[0] to the D input pin of DFF out[4]. This will cauing LEC "compare" fail (while map still ok).
I have used the "set flatten model -seq_merge" option in LEC, which still occured this problem.
Of caue, the RTL code isn't well codec, whie there must be many places with the same case, so I can't manully set equivalen in LEC.

My question is: Have you ever met this problem before and how will you solve the problem (except change the RTL cdoe ^_^).

Thanks.

 

[ebuddy]

"...so DC may connect the DFF Q ouput of a[0] to the D input pin of DFF out[4]. This will cauing LEC "compare" fail... " I think DC did the right thing. Why would this cause LEC to fail?

 

[lostinxlation]

I think DC did the right thing. Why would this cause LEC to fail?

LEC would fail unless it can look beyond the flops, which, per my understanding, is not implemented in LEC. I think the quick solution is just setting equivalency to those registers or modifying the RTLs to eliminate those redundant flops(flops having the same value all the time is technically redundant).

 

[yx.yang]

LEC would fail unless it can look beyond the flops, which, per my understanding, is not implemented in LEC. I think the quick solution is just setting equivalency to those registers or modifying the RTLs to eliminate those redundant flops(flops having the same value all the time is technically redundant).

Hi, lostinxlation:
Thanks or your reply.
Change RTL of cause is a good way. While LEC must be at the end of one project, how dare I change RTL at this stage. I'm looking for any options in LEC. Thanks.

 

[sp]

read the LEC command reference, try to find "set instance equivalent".
i am not really visualizing your RTL vs. synthesis, but i can feel that this is what u need.

instance equivalent is when u have duplicate or merging of DFF.

netlist A
reg a -> reg b -> reg c
reg a -> reg x -> reg y

netlist B
reg a -> reg m -> reg c
reg a -> reg m -> reg y

if u want to LEC these 2 netlist, u need to map either reg m to reg b or reg x, then use "set instance equivalent" to reg b and reg x.