rtl case statement
analog_fever said:
I am not sure if you know what you are talking about. If store_var is declared as a reg variable is it not supposed to hold its previous value, if it is not defined in the present "case" state? Why would it take the default value when there is actually a valid case state.
Reg variables are not always mapped into sequential logic. If your always block has a clock in the sensativity list, they will become a flip-flop and store the value. In a non-clocked always block they can be combinational if given values in all cases (or given a default case) OR they can become latches (not FFs) if not given values in all cases.
In your case, it looks like store_var should be inferring a latch, but this is normally not good practice. It's best to keep your unclocked always blocks as combinational and assign nets default values as mentioned above to avoid latched. For the store_var reg you can put it in a separate clocked always block.
always @(posedge clk or negedge rst) begin
if (!rst)
store_var <= 1'b0;
else if (state == B)
store_var <= some_parameter;
end
An even better approach would be to define a combinational net (store_var_next) and assign it values for every case (or give it a default) in your combinational always block. Something like this ...
always@* begin
store_var_next = store_var;
case(state)
B: store_var_next = some_parameter;
C: assign store_var_next again here or let it use default above case statement
........
end
always @(posedge clk or negedge rst) begin
if (!rst)
store_var <= 1'b0;
else
store_var <= store_var_next;
end