RTL Functional simulation

[vishwa]

rtl simulation with timing

Hi,

I have better knowledge in RTL design in using Verilog/VHDL. Worked in multiple projects.

But I am very new to functional simulation of RTL description. I have few questions on how design a testbench setup.

1. What are the considerations while designing testbench.

2. How to check the internal signals of a design

3. How to check the full functionality of a RTL design, if it has multiple functionalities.

4. What is timing simulation. How come it ispossible to check timing at RTL design level. I think timing can be verifed once the gate netlist is generated.

Please help me in this regard. Please let me know is there any book/tutor to learn about the RTL simulation.


Thanks in advance,

Viswa

 

[emil1985]

Hi,

Here is list of some books that may help you:

Writing Testbenches: Functional Verification of HDL Models, Second Edition by Janick Bergeron

Writing Testbenches using SystemVerilog by Janick Bergeron

You can find second book on internet in pdf, but probably it's going to be copy of book.

Best regards.

 

[sree205]

Hopefully, these answers will be a starting point for ur questions.

1. What are the considerations while designing testbench.
To ensure that functionality for which the RTL is coded is checked properly and to ensure that all parts of the RTL are checked. This is done by means of writing "functional coverage points" and by ensuring that code coverage is 100%

2. How to check the internal signals of a design
In some designs, the internal signals are not checked at all. This is called black box method of verification. Incase if its necessary to check the internal signals, the best possible way to do is to access it using hierarchical method in verilog.

e.g : if instance of a module is u_add, and if there is an signal called x, which is passed on to some other module, its possible to either display it in the TB or assign it to a signal in the top level module this way.

assign x = (u_add.x)

3. How to check the full functionality of a RTL design, if it has multiple functionalities.

either write directed testcases catering to one functionality at a time or write a random testcase by providing constraints such that only the functionalities to be checked will be hit.

4. What is timing simulation. How come it ispossible to check timing at RTL design level. I think timing can be verifed once the gate netlist is generated.

timing simulation is done with the help of netlist only. also called gate level simulation, it takes into account the delay associated with the particular gates that are there in the netlist and drives the stimulus to the DUT as before. This is an exhaustive method of checking for timing. Inplace of this, static timing analysis is used these days, where stimulus is not provided, but timing is checked by means of timing arcs.

Comments and corrections are welcome.

 

[saikat]

1. First design a verification environment (packages with required procedures and functions, portmaps, architecture configurations etc.) which will connect to your DUT and have an interface for connecting the test cases. Then design test cases to test varius functionalities of the DUT.

2. If you are using ModelSim, it will show all the available signals behaviour. But verifying signal behaviour for functional testing is not a good practice, you should have a text based verbose test bench which generated the test results as a text file and you can determine the test results by viewing the report file. If some thing goes wrong, then consult the waveforms.

3. You have to design directed test cases to verify each functionality of the DUT if you are using VHDL/Verilog. They dont have random stimulus generation feature like SystemVerilog.

4. Timing simulation is enhanced functional simulation with the gate delays of the device were taken into account. For xilinx devices, you have to generate .sdf file in ISE for running timing simulation in ModelSim. Modelsim will not show you the internal signals behaviour while running timing simulation.

Good Luck with verification