rtl compiler synthesis generated netlist simulation

[swaps]

Hi frnds,
Can anybody tell me how we simulate netlist(gate level) file after doing rtl-gate level synthesis.
I m using cadence rtl compiler for synthesis of standard cells in verilog. After doing successful synthesis it generates gate level netlist which i have to simulate to verify the functionality of standard cells. Simulator is ncSim.

When i trying to simulate it shows error with all individual cells. And can't get that errors.

Looking for positive response from anyone.

Thanx.

 

[kornukhin]

Post error log here.
DId you compile standard cells simulation library in NCSim?

 

[raghavathej]

Just compile the library which contains functional defination of each gates.
I am sure you are using TSMC library.
So, compiler tsmc_180.v file first before compiling the netlist
Then elaborate the testbench(NCelab) but before that provide timescale for netlist and testbench.
Then Simulate the testbench.
If you dont use verilog library of the equivalent cells of that of fast/slow/typical .lib file then during compiling
the compiler cannot understand the cell defination as netlist will be in the structural form.