I was thinking about an RTL auto code generation based on parsing existing code. Suppose for example that I have a list of modules and each of them has some test ports. I want to be able to parse all this modules collect all this test signals and crate a new module (at least top level in the beginning) which will include all those signals. What would be the best solution for this (scripting, language, tool)? For example I was thinking Python or bash scripting but I would like to hear other opinions.
Python should be fine, perl too. If you need to understand the full syntax of a verilog file then go with something more complex like lex/yacc parse in C++.
Well scripting in any language should be fine, however, there are licensed tools from synopsys to generate top level RTL and provide connectivity solution as well. Tool name is synopsys coreTool.
However, that being said for a smaller project, scripting should be fine. Limitation will be making the script versatile enough to understand all Verilog and SystemVerilog syntax and making it future proof.