Round Robin Arbiter using verilog help

[Selvakumaran_007]

Hi,

I am working on designing a round robin arbiter(4 devices -two bit grant output) using verilog. I am assuming four states, in each state there is an assumed priority among the four devices and depending on the device acknowledgement received the fsm will go to the state where the device which previously used the control has the least priority in the next cycle. I had a thought supposing I'm in a state and there are no requests from any of the device should I make the fsm stay in the same state or shall I have a counter which counts some 'n' number of cycles within which if there are no requests coming from the devices would mean the fsm would go to the next state where a different device would get a higher priority. My thought was if I changed states and if no requests comes for a while it will give another device a shot at a higher priority. Isn't round robin supposed to do that give all devices equal priority and pass the token?
Thank you,

Selvakumaran

 

[achaleus]

Round robin works as you say... whether you go to the next state (after waiting for some clock cycles if there is no request) or in the same state depending on requirement but both come under round robin

 

[rahul7456]

In round robin the counter is must..Orelse it will hang..Also all 3 request should have equal value in counter..