I want to estimate the aria of the layout of my circuit. I know the size of transistors but I don't know the size of the aria to be occupied by routing signals and power.
Please can any one help me how I can estimate the aria of my circuit.
Most layouts are bond pad limited. So if you know how many bondpads the design will use then the chip area is normally dominated by this unless you are using solder bump pads distributed over the layout.