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ROM design for built in self test

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ASHA PON

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I am working with C432 benchmark circuits. I am trying to write Verilog code to store fault free outputs of the circuit for 2^36 input test vectors in a ROM. It is taking more than 3 days to write all the address. Can you please guide me whether my approach is correct or not. If not, can you suggest me to shorten the code.
 

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