role of static timing analysis tools in Design process

[ar_m_in]

hello all

I am new into this area, can you guys please tell me the role of STA tools in an FPGA flow please

any good books or suggestions on picking up static timing analysis in FPGA's in general

thanks a lot

 

[Iouri]

simple idea is to make sure set up and hold time are meet for different scenarios,

 

[ar_m_in]

thanks a lot

I will go through Chapter 13 of that link

however most of the matter on Chapter 13 had references to Prime Time, is there anything which is more general

thanks for help

 

[Iouri]

prime time is Synpsys software for the ASIC, and there is something what it call SDC format, now for example if you constrining ALtera FPGA you are using DSC format. Also SDC it is standard de fact format in most FPGA/ASIC developments

 

[wangkaust]

go to Xilinx or Altera website or look for some technical training materials from them

 

[ar_m_in]

thanks Iouri and wangkaust

 

[hemal]

sta material\]