you could, but I would not recommend it. The rising/falling_edge functions treat the input as a clock, and in an FPGA you're only allowed to evaluate a single clock in any process.
It would be much better to have a system clock and a synchroniser on your switch (ie, sample the switch with the clock through a double register) and then do a rising edge detect on that.
What TrickyDicky said. Besides the standard drawbacks of using a regular input as a clock input, you have the extra bonus drawback of this switch being mechanical. And as such you'll probably want some debouncing. So as said you use a synchroniser on the switch input, and then do the edge detection after that.
thank for all for suggestion
but is thier a vhdl code for this words
""""It would be much better to have a system clock and a synchroniser on your switch (ie, sample the switch with the clock through a double register) and then do a rising edge detect on that.???"""
What TrickyDicky and mrflibble said is correct. it will consider as clock. To avoid that you can use like below,
Let we consider signal which to be detected is a. Then make a delay wrt clock.Then delayed signal is a_delayed.
now to detect rising edge, if( a= '1' and a_delayed ='0')then.
to detect falling edge if( a= '0' and a_delayed ='1')then.