I am new to VHDL so please help me
There are two signals RESET and IN. How should the sensitivity list look like
if a method should be called on a rising edge of IN and on every change of
RESET?
I know about the sensitivity list and I understood the change of RESET also but what mean RISING EDGE OF IN.
Please help me to understand this
Thanks
IN is an input pin and rising edge means when pulse goes from low to high. It is the transition from low to high state or in 5V TTL logic level it is transition from 0 to 5V.
Then it would be an active high synchronous reset register with a rising edge clock.
If the IN signal is an input pin (as milan.rajik says) and is going directly to the clock pin of a register, then it better be a clean input with well defined transitions, otherwise you may end up with a circuit that has "glitches".
And that rising_edge thing is a function:
Code VHDL - [expand]
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FUNCTION rising_edge (SIGNAL s :std_ulogic)RETURNBOOLEANISBEGINRETURN(s'EVENTAND(To_X01(s)= '1')AND(To_X01(s'LAST_VALUE)= '0'));END;