RISC processor design in verilog

I m desiging a 8 bit risc processor...All the modules in it are working but when i m tring to make the whole module RISC it was not working as i dont know how to enter the data inside the memory block and wht should be the input and output pins in the whole processor............

When i run the following test bench code.........
module test_risc_spm55 ();
reg rst;
wire clk;
parameter word_size = 8;
reg [8:0] k;
reg [7:0] memory [254:0];
//reg [word_size-1:0]r0_out;

Clock_Unit M1 (clk);
risc_spm M2 (clk, rst);


wire [word_size-1:0] word180, word181, word182, word183;
wire [word_size-1:0] word240, word241;

assign word180 = M2.m2_mem.memory[180];
assign word181 = M2.m2_mem.memory[181];
assign word182 = M2.m2_mem.memory[182];
assign word183 = M2.m2_mem.memory[183];
assign word240 = M2.m2_mem.memory[240];
assign word241 = M2.m2_mem.memory[241];


initial #2500 $finish;

initial fork
#0 for (k=0;k<=255;k=k+1)M2.m2_mem.memory[k]=0; rst = 1;
#2 $readmemh ("prog1.mem",M2.m2_mem.memory);
#5 rst = 0;
#15 rst = 1;
join

endmodule


The result says that ---Failed to find 'm2_mem' in hierarchical name.

Even though i defined it in the topmodule........