Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

RISC has logical 5 stage pipeline, why do some processors have much more stages?

Status
Not open for further replies.

matrixofdynamism

Advanced Member level 2
Joined
Apr 17, 2011
Messages
565
Helped
24
Reputation
48
Reaction score
23
Trophy points
1,298
Activity points
7,369
I have read this marvelous book on processor architecture. It teaches that:

The classic RISC pipeline comprises:
Instruction fetch
Instruction decode and register fetch
Execute
Memory access
Register write back


Now wikipedia says that:
•Many designs include pipelines as long as 7, 10 and even 20 stages (as in the Intel Pentium 4).
•The later "Prescott" and "Cedar Mill" Netburst cores from Intel, used in the latest Pentium 4 models and their Pentium D and Xeon derivatives, have a long 31-stage pipeline.

How can a pipeline be so long? I am in awe and lost as to why we need such long pipelines. Do all instructions need such long pipelines?

Also, since MIPS may implement FPU as well in a coprocessor, how does that effect the 5-stage pipeline? I don't think that a floating point calculation can be complete within a single clock cycle for execute stage.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top