Ripple Carry Adder using Structural Modeing

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity ripple is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           c : in  STD_LOGIC;
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           co : out  STD_LOGIC);
end ripple;
 
architecture Behavioral of ripple is
component fulladd
port(a,b,cin:in STD_LOGIC;cout,sum:out STD_LOGIC);
end component;
 
signal cc:STD_LOGIC_VECTOR(3 downto 1);
begin
 
fa0:fulladd port map(x(0),y(0),c,s(0),cc(1));
fa1:fulladd port map(x(1),y(1),cc(1),s(1),cc(2));
fa2:fulladd port map(x(2),y(2),cc(2),s(2),cc(3));
fa3:fulladd port map(x(3),y(3),cc(3),s(3),co);
end Behavioral;

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
entity fulladd is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end fulladd;
 
architecture Behavioral of fulladd is
 
begin
sum<=a xor b xor cin;
cout<=(a and b) or (b and cin) or (a and cin);
 
end Behavioral;