[SOLVED] right shift operation in verilog

[dipin]

hi,
i need to do parallel in parallel out right shift operation(in fpga).
in code it is >> . but problem is did anybody know what is the hardware for shift operation . i searched in internet ,one is using 2:1 multiplexer, can i do it using d flipflop, if it possible please give some idea.please give your valuable suggestion..

thanks & regards

 

[rahul.achates]

Without register or flop , you can not perform shift operation.

Give more detail on this , like block diagram ..

 

[FvM]

Without register or flop , you can not perform shift operation.

Give more detail on this , like block diagram ..

A shift operation can be well performed in combinational expressions and won't use registers respectively. Clock synchronous sequential shifts using registers are possible, too. The question is about the specification.

A constant shift doesn't even need a multiplexer just wires.

 

[rahul.achates]

I agree .. its depend on specification. but for Shift , dependent signals has to be flopped.

 

[dipin]

Give more detail on this , like block diagram ..

thanks for the replay.
i need to do 1 bit shift to the right for each clock cycle and need to perform this in fpga.did any one know what is the hardware for this in fpga . for each shift i need to add zero to the left side and output the data . for code it is >>,but dont know what is the hardware for the right shift in fpga (inputs are stored in a register and need to perform right shift n times to the same input. after each shift i need to show output)

thanks and regards

 

[ads-ee]

Verilog:

always @(posedge clk)
  sdata  <= {1'b0, sdata[MAX_INDX:1]};

VHDL:

process (clk)
  if rising_edge (clk) then
    sdata <= '0' & sdata(MAX_INDX downto 1);
  end if;

fixed the '1' to the '0', as OP wanted to shift in 0's

 

[dipin]

thanks ads-ee