the variable _rPackedCount is not reset to zero . Why ?
I think the logic assumes flush will not occur if the count > 3 or if there is valid input on the same cycle.
it does make assumptions about flush and valid data on the same cycle though.
You have two conflicting sentences from two of your separate posts.
Code Verilog - [expand] 1 2 3 4 5 // Shift data into and out of our buffer as we receive and write out data. if (rDataMaskedEn != 3'd0) _rPackedData = ((rPackedData>>(32*{rPackedCount[2], 2'd0})) | (rDataMasked<<(32*rPackedCount[1:0]))); else _rPackedData = (rPackedData>>(32*{rPackedCount[2], 2'd0}));
a flush + a write that results in _count > 4 if count != 4 or _count !=4 if count = 4. or maybe just flush + valid input.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 /* verilator lint_off UNOPTFLAT */ module reg_pipeline #( parameter C_DEPTH = 10, parameter C_WIDTH = 10 ) ( input CLK, input RST_IN, input [C_WIDTH-1:0] WR_DATA, input WR_DATA_VALID, output WR_DATA_READY, output [C_WIDTH-1:0] RD_DATA, output RD_DATA_VALID, input RD_DATA_READY ); genvar i; wire wReady [C_DEPTH:0]; reg [C_WIDTH-1:0] _rData [C_DEPTH:1], rData [C_DEPTH:0]; reg _rValid [C_DEPTH:1], rValid [C_DEPTH:0]; // Read interface assign wReady[C_DEPTH] = RD_DATA_READY; assign RD_DATA = rData[C_DEPTH]; assign RD_DATA_VALID = rValid[C_DEPTH]; // Write interface assign WR_DATA_READY = wReady[0]; always @(*) begin rData[0] = WR_DATA; rValid[0] = WR_DATA_VALID; end generate for( i = 1 ; i <= C_DEPTH; i = i + 1 ) begin : gen_stages assign #1 wReady[i-1] = ~rValid[i] | wReady[i]; // Data Registers always @(*) begin _rData[i] = rData[i-1]; end // Enable the data register when the corresponding stage is ready always @(posedge CLK) begin if(wReady[i-1]) begin rData[i] <= #1 _rData[i]; end end // Valid Registers always @(*) begin if(RST_IN) begin _rValid[i] = 1'b0; end else begin _rValid[i] = rValid[i-1] | (rValid[i] & ~wReady[i]); end end // Always enable the valid registers always @(posedge CLK) begin rValid[i] <= #1 _rValid[i]; end end endgenerate endmodule /* verilator lint_on UNOPTFLAT */
back-pressure at only the destination
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