REVIEW JPEG-2000 Architecture DESIGN

Final Results
RTL Top Level Output File Name : feed.ngr
Top Level Output File Name : feed
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

Design Statistics
# IOs : 10

Cell Usage :
# BELS : 48861
# GND : 2
# INV : 402
# LUT1 : 57
# LUT2 : 13342
# LUT3 : 2619
# LUT4 : 329
# LUT5 : 311
# LUT6 : 1016
# MUXCY : 15969
# MUXF7 : 20
# VCC : 2
# XORCY : 14792
# FlipFlops/Latches : 1056
# FDC : 32
# FDCE : 512
# FDE : 512
# RAMS : 1
# RAMB18 : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 9
# IBUF : 1
# OBUF : 8
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Device utilization summary:
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Selected Device : 5vlx110tff1136-1


Slice Logic Utilization:
Number of Slice Registers: 1056 out of 69120 1%
Number of Slice LUTs: 18076 out of 69120 26%
Number used as Logic: 18076 out of 69120 26%

Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 18515
Number with an unused Flip Flop: 17459 out of 18515 94%
Number with an unused LUT: 439 out of 18515 2%
Number of fully used LUT-FF pairs: 617 out of 18515 3%
Number of unique control sets: 68

IO Utilization:
Number of IOs: 10
Number of bonded IOBs: 10 out of 640 1%

Specific Feature Utilization:
Number of Block RAM/FIFO: 1 out of 148 0%
Number using Block RAM only: 1
Number of BUFG/BUFGCTRLs: 1 out of 32 3%


Timing Summary:
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Speed Grade: -1

Minimum period: 26.726ns (Maximum Frequency: 37.417MHz)
Minimum input arrival time before clock: 3.567ns
Maximum output required time after clock: 6.560ns
Maximum combinational path delay: No path found

# Adders/Subtractors : 954
# Counters : 1
# Registers : 140
# Comparators : 3
# Multiplexers : 1

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